                    I2C SerialEPROM  Reference Design
=====================================================================================================

 1. /rd1006/docs/rd1006.pdf                         --> I2C design document
    /rd1006/docs/rd1006_readme.txt                  --> Read me file (this file)
    /rd1006/docs/i2cspec1.pdf                       --> I2C spec
    
 2. 



    /rd1006/project/xo3l/verilog/xo3l_verilog.ldf	    --> Lattice Diamond project file  for verilog
    /rd1006/project/xo3l/verilog/xo3l_verilog.lpf       --> preference file   for verilog           
    /rd1006/project/xo3l/verilog/xo3l_verilog.sty      --> strategy file  for verilog   
    
    /rd1006/project/xo3l/vhdl/xo3l_vhdl.ldf	            --> Lattice Diamond project file  for vhdl
    /rd1006/project/xo3l/vhdl/xo3l_vhdl.lpf             --> preference file   for vhdl          
    /rd1006/project/xo3l/vhdl/xo3l_vhdl.sty            --> strategy file  for vhdl  



    /rd1006/project/xo/verilog/xo_verilog.ldf	    --> Lattice Diamond project file  for verilog
    /rd1006/project/xo/verilog/xo_verilog.lpf       --> preference file   for verilog           
    /rd1006/project/xo/verilog/xo_verilog.sty      --> strategy file  for verilog   
    
    /rd1006/project/xo/vhdl/xo_vhdl.ldf	            --> Lattice Diamond project file  for vhdl
    /rd1006/project/xo/vhdl/xo_vhdl.lpf             --> preference file   for vhdl          
    /rd1006/project/xo/vhdl/xo_vhdl.sty            --> strategy file  for vhdl  




    /rd1006/project/xo2/verilog/xo2_verilog.ldf	    --> Lattice Diamond project file  for verilog
    /rd1006/project/xo2/verilog/xo2_verilog.lpf       --> preference file   for verilog           
    /rd1006/project/xo2/verilog/xo2_verilog.sty      --> strategy file  for verilog   
    
    /rd1006/project/xo2/vhdl/xo2_vhdl.ldf	            --> Lattice Diamond project file  for vhdl
    /rd1006/project/xo2/vhdl/xo2_vhdl.lpf             --> preference file   for vhdl          
    /rd1006/project/xo2/vhdl/xo2_vhdl.sty            --> strategy file  for vhdl  




    

/rd1006/project/ecp3/verilog/ecp3_verilog.ldf	    --> Lattice Diamond project file  for verilog
    /rd1006/project/ecp3/verilog/ecp3_verilog.lpf       --> preference file  for verilog           
    /rd1006/project/ecp3/verilog/ecp3_verilog.sty      --> strategy file  for verilog   
    
    /rd1006/project/ecp3/vhdl/ecp3_vhdl.ldf	            --> Lattice Diamond project file  for vhdl
    /rd1006/project/ecp3/vhdl/ecp3_vhdl.lpf             --> preference file   for vhdl          
    /rd1006/project/ecp3/vhdl/ecp3_vhdl.sty            --> strategy file  for vhdl  



/rd1006/project/ecp5/verilog/ecp5_verilog.ldf	    --> Lattice Diamond project file  for verilog
    /rd1006/project/ecp5/verilog/ecp5_verilog.lpf       --> preference file   for verilog           
    /rd1006/project/ecp5/verilog/ecp5_verilog.sty      --> strategy file  for verilog   
    
    /rd1006/project/ecp5/vhdl/ecp5_vhdl.ldf	            --> Lattice Diamond project file  for vhdl
    /rd1006/project/ecp5/vhdl/ecp5_vhdl.lpf             --> preference file   for vhdl          
    /rd1006/project/ecp5/vhdl/ecp5_vhdl.sty            --> strategy file  for vhdl  







    
 3. /rd1006/simulation/xo2/verilog/rtl_verilog.do	    --> RTL simulation script file for verilog for xo2  
    /rd1006/simulation/xo2/verilog/timing_verilog.do	    --> Timing simulation script file for verilog for xo2

    /rd1006/simulation/xo2/vhdl/rtl_vhdl.do		    --> RTL simulation script file for vhdl for xo2     
    /rd1006/simulation/xo2/vhdl/timing_vhdl.do              --> Timing simulation script file for vhdl for xo2 





    /rd1006/simulation/xo3l/verilog/rtl_verilog.do          --> Verilog RTL simulation script for xo3l
    /rd1006/simulation/xo3l/verilog/timing_verilog.do   --> Verilog TIMING simulation script for xo3l
   
    /rd1006/simulation/xo3l/vhdl/rtl_vhdl.do                --> VHDL RTL simulation script for xo3l
    /rd1006/simulation/xo3l/vhdl/timing_vhdl.do         --> VHDL TIMING simulation script for xo3l



    /rd1006/simulation/xo/verilog/rtl_verilog.do          --> Verilog RTL simulation script for xo
    /rd1006/simulation/xo/verilog/timing_verilog.do   --> Verilog TIMING simulation script for xo
   
    /rd1006/simulation/xo/vhdl/rtl_vhdl.do                --> VHDL RTL simulation script for xo
    /rd1006/simulation/xo/vhdl/timing_vhdl.do         --> VHDL TIMING simulation script for xo



/rd1006/simulation/xp2/verilog/rtl_verilog.do          --> Verilog RTL simulation script for xp2
    /rd1006/simulation/xp2/verilog/timing_verilog.do   --> Verilog TIMING simulation script for xp2
   
    /rd1006/simulation/xp2/vhdl/rtl_vhdl.do                --> VHDL RTL simulation script for xp2
    /rd1006/simulation/xp2/vhdl/timing_vhdl.do         --> VHDL TIMING simulation script for xp2



/rd1006/simulation/ecp3/verilog/rtl_verilog.do          --> Verilog RTL simulation script for ecp3
    /rd1006/simulation/ecp3/verilog/timing_verilog.do   --> Verilog TIMING simulation script for ecp3
   
    /rd1006/simulation/ecp3/vhdl/rtl_vhdl.do                --> VHDL RTL simulation script for ecp3
    /rd1006/simulation/ecp3/vhdl/timing_vhdl.do         --> VHDL TIMING simulation script for ecp3
 


/rd1006/simulation/ecp5/verilog/rtl_verilog.do          --> Verilog RTL simulation script for ecp5
    /rd1006/simulation/ecp5/verilog/timing_verilog.do   --> Verilog TIMING simulation script for ecp5
   
    /rd1006/simulation/ecp5/vhdl/rtl_vhdl.do                --> VHDL RTL simulation script for ecp5
    /rd1006/simulation/ecp5/vhdl/timing_vhdl.do         --> VHDL TIMING simulation script for ecp5
 
  

    
 		
 4. /rd1006/source/verilog/i2c.v                    --> verilog source file - top level
    /rd1006/source/verilog/i2c_clk.v                --> verilog source file
    /rd1006/source/verilog/i2c_rreg.v               --> verilog source file
    /rd1006/source/verilog/i2c_wreg.v               --> verilog source file
    /rd1006/source/verilog/i2c_st.v                 --> verilog source file

    /rd1006/source/vhdl/i2c.vhd                     --> vhdl source file - top level
    /rd1006/source/vhdl/i2c_clk.vhd                 --> vhdl source file
    /rd1006/source/vhdl/i2c_rreg.vhd                --> vhdl source file
    /rd1006/source/vhdl/i2c_wreg.vhd                --> vhdl source file
    /rd1006/ource/vhdl/i2c_st.vhd                  --> vhdl source file








    
 5. /rd1006/testbench/verilog/i2c_tb.v              --> Testbench for verilog simulation - top-level
    /rd1006/testbench/verilog/micro.v               --> Testbench for verilog simulation
    /rd1006/testbench/verilog/i2c_slave.v           --> Testbench for verilog simulation
    /rd1006/testbench/verilog/clk_rst.v             --> Testbench for verilog simulation

    /rd1006/testbench/vhdl/i2c_tb.vhd               --> Testbench for vhdl simulation 

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!!IMPORTANT NOTES:!!
1. Unzip the rd1006_revyy.y.zip file using the existing folder names, where yy.y is the current
   version of the zip file
2. If there is lpf file or lci file available for the reference design:
	2.1 copy the content of the provided lpf file to the <project_name>.lpf file under your ispLEVER project, 
	2.2 use Constraint Files >> Add >> Exiting File to import the lpf to Diamond project and set it to be active,
	2.3 copy the content of the provided lct file to the <project_name>.lct under your cpld project.  
3. If there is sty file (strategy file for Diamond) available for the design, go to File List tab on the left 
   side of the GUI. Right click on Strategies >> Add >> Existing File. Then right click on the imported file 
   name and select "Set as Active Strategy".

===================================================================================================  
Using ispLEVER or ispLEVER Classic software
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HOW TO CREATE A ISPLEVER OR ISPLEVER CLASSIC PROJECT:
1. Bring up ISPLEVER OR ISPLEVER CLASSIC software, in the GUI, select File >> New Project
2. In the New Project popup, select the Project location, provide a Project name, select Design Entry Type 
   and click Next.
3. Use rd1006.pdf to see which device /speedgrade should be selected to achieve the desired timing result
4. Add the necessary source files from the rd1006\source directory, click Next
5. Click Finish. Now the project is successfully created. 
6. Make sure the provided lpf or lct is used in the current directory. 

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HOW TO RUN SIMULATION FROM ISPLEVER OR ISPLEVER CLASSIC PROJECT:
1. Import the top-level testbench into the project as test fixture and associate with the device
	1.1 Import the rest as Testbench Dependency File by highligh and right click on the test bench file
2. In the Project Navigator, highlight the testbench file on the left-side panel, user will see 3 
   simulation options on the right panel.
3. For functional simulation, double click on Verilog (or VHDL) Functional Simulation with Aldec 
   Active-HDL. Aldec simulator will be brought up, click yes to overwrite the existing file. The 
   simulator will initialize and run for 1us.
4. Type "run -all" for verilog in the Console panel. A script similar to this 
   will be in the Console panel:
 
 i2c_tb.SEP Using 7 Bit Addressing 
      510: Coming out of Reset

      510: Writing Word Address
      540: Simulation Starting

   103095 i2c_tb.SEP << 7 bit addressing & address is 10100000 >>
   185025 i2c_tb.SEP << Slave Data Received on write is 01010101 >>
   307905 i2c_tb.SEP << 7 bit addressing & address is 10100001 >>
   394935 i2c_tb.SEP << Slave Data transmitted on read is 01010101 >>
   394935 i2c_tb.SEP No ACK on a Data Read, returning to Idle
   412270 leaving monitor
   413270: Reading Data
   413310: Data = 55
   423310: Writing Word Address
   525855 i2c_tb.SEP << 7 bit addressing & address is 10100000 >>
   607785 i2c_tb.SEP << Slave Data Received on write is 10101010 >>
   730665 i2c_tb.SEP << 7 bit addressing & address is 10100001 >>
   817695 i2c_tb.SEP << Slave Data transmitted on read is 10101010 >>
   817695 i2c_tb.SEP No ACK on a Data Read, returning to Idle
   835030 leaving monitor
   836030: Reading Data
   836070: Data = aa
   836070 << Simulation complete with           0 errors >>
# RUNTIME: RUNTIME_0070 micro.v (150): $stop called.
5. For timing simulation, double click on Verilog (or VHDL) Post-Route Timing Simulation with Aldec 
   Active-HDL. Similar message will be shown in the console panel of the Aldec Active-HDL simulator.
   5.1 Run -all to see the complete simulation
   5.1 In timing simulation you may see some warnings about narrow widths or vital glitches. These 
       warnings can be ignored. 
   5.2 Vital glitches can be removed by added a vsim command in the udo file. Use the udo.example 
       under the \project directory
   
===================================================================================================  
Using Diamond Software
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HOW TO CREATE A PROJECT IN DIAMOND:
1. Launch Diamond software, in the GUI, select File >> New Project, click Next
2. In the New Project popup, select the Project location and provide a Project name and implementation 
   name, click Next.
3. Add the necessary source files from the rd1006\source directory, click Next
4. Select the desired part and speedgrade. You may use rd1006.pdf to see which device and speedgrade 
   can be selected to achieve the published timing result 
5. Click Finish. Now the project is successfully created. 
6. MAKE SURE the provided lpf and/or sty files are used in the current directory. 
      
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HOW TO RUN SIMULATION UNDER DIAMOND:
1. Bring up the Simulation Wizard under the Tools menu 
2. Next provide a name for simulation project, and select RTL or post-route simulation
	2.1 For post-route simulation, must export verilog or vhdl simulation file after Place and Route
3. Next add the test bench files form the rd1006\TestBench directory 
	3.1 For VHDL, make sure the top-level test bench is last to be added
4. Next click Finish, this will bring up the Aldec simulator automatically
5. In Aldec environment, you can manually activate the simulation or you can use a script
	5.1 Use the provided script in the rd1006\Simulation\<language> directory
	        a. For functional simulation, change the library name to the device family
	  	   i) MachXO2: ovi_machxo2 for verilog, machxo2 for vhdl
	  	   ii) MachXO: ovi_machxo for verilog, machxo for vhdl
	  	   iii) XP2: ovi_xp2 for verilog, xp2 for vhdl
                   iv) ECP3: ovi_ecp3 for verilog, ecp3 for vhdl
                   v) XO3L: ovi_machxo3l for verilog, machxo3l for vhdl 
			iv) ECP5 : ovi_ecp5u for verilog, ecp5u for vhdl
	        b. For POST-ROUTE simulation, open the script and change the following:
			i) The sdf file name and the path pointing to your sdf file.
		   The path usually looks like "./<implementation_name>/<sdf_file_name>.sdf"
		  ii) Change the library name using the library name described above
	        c. Click Tools > Execute Macro and select the xxx.do file to run the simulation
	        d. This will run the simulation until finish
	5.2 Manually activate the simulation
		a. Click Simulation > Initialize Simulation, and select top testbench file.
		b. Click File > New > Waveform, this will bring up the Waveform panel
		c. Click on the top-level testbench, drag all the signals into the Waveform panel
		d. At the Console panel, type "run -all" for VHDL simulation, or "run -all" for Verilog 
		   simulation
		e. For timing simulation, you must manually add 
		   -sdfmax i2c_top="./final_xo2/final_xo2_final_xo2_vo.sdf"
		   into the asim or vsim command. Use the command in timing_xxx.do as an example
6. The simulation result will be similar to the one described in ispLEVER simulation section. 

